The present invention relates to integrated circuits, and more particularly to methods and structures incorporating fluorine-containing dielectrics and fluorine diffusion barriers therein.
Steady increases in the operating speeds of integrated circuits have arisen from decreasing transistor dimensions. In particular, smaller transistor gate lengths result in improved intrinsic gate delay, and, therefore, faster transistor switching times. However, as gate delay decreases, interconnect or xe2x80x9cRCxe2x80x9d delay increases, due to increased wiring capacitance. Thus, for transistors having device features less than about 0.25 xcexcm, circuit performance becomes limited by RC delay rather than by gate delay. To improve interconnect performance and decrease RC delay, integrated circuit manufacturers now modify circuit design techniques, such as by limiting the wire length and by adding repeaters along long interconnect nodes. However, while these modifications reduce current interconnect delay problems, additional scaling down will require new methods and/or materials to reduce the interconnect resistance and capacitance.
At feature sizes below about 0.25 xcexcm, it may be necessary to incorporate other materials into the transistor structure to minimize RC delay and to improve device performance. For example, existing interconnect metals, typically Al or an Al alloy, can be replaced with another metal, such as Cu, which has a resistivity (xe2x80x9cRxe2x80x9d) about 35% lower than that of aluminum. Alternatively, or in combination therewith, the existing dielectric, typically silicon dioxide (SiO2), which has a dielectric constant of 4.0, can be replaced with a material having a lower dielectric constant, thereby providing a lower capacitance (xe2x80x9cCxe2x80x9d).
Of solid dielectric materials, fluorinated polymers have the lowest dielectric constants (as low as 1.9), and thus, confer the largest decreases in RC delay. However, one of the drawbacks to integrating fluorinated polymers into semiconducting devices is the instability of the fluorine. Fluorine has a tendency to diffuse out of the polymer and migrate into the adjacent interconnect metal. Therefore, in order to incorporate fluorine-containing dielectrics into semiconducting devices, a fluorine diffusion barrier must also be incorporated into the structure to separate the dielectric from the interconnect. However, such a diffusion barrier which can effectively stop fluorine migration at high processing temperatures is not available in the prior art.
Based on the above discussion, it is clear that as the dimensions of transistor devices decrease, it will become more and more desirable to incorporate fluorinated polymers into integrated circuit structures. These materials have low dielectric constants, making them attractive for lowering the RC delay, and therefore maximizing the operating speed. In order to use fluorinated dielectrics, it is clear that a need exists for diffusion barriers that can halt fluorine diffusion effectively. Furthermore, to be useful, such fluorine diffusion barriers should be thin. In addition, the barriers should have a low resistivity and/or low dielectric constant, so as not to diminish the gains attained by utilizing advanced interconnect and/or dielectric materials. Also, the diffusion barrier should be thermally stable over time so as to withstand high processing temperatures up to about 450xc2x0 C.
The present invention fulfills the aforementioned needs and requirements by providing suitable and effective fluorine-diffusion barrier materials. Thus, the advantages of incorporating fluorine-containing dielectric polymers into semiconducting devices can now be realized. In addition, the present diffusion barriers are useful in connection with most fluorinated dielectrics and therefore the utility of such barriers is not limited by the particular dielectric being used.
Surprisingly, it has now been discovered that doped or undoped silicon when combined with tantalum or cobalt can be used as a fluorine diffusion barrier when positioned adjacent a fluorinated dielectric. Such a barrier layer stops fluorine atoms from diffusing into an overlying or underlying interconnect, even after thermal cycling at temperatures reaching 450xc2x0 C. during subsequent chip fabrication processes.
Accordingly, the present invention provides structures and methods for preventing fluorine from diffusing out of a fluorine-containing dielectric and into an adjacent interconnect in an integrated circuit structure. As used herein, xe2x80x9cinterconnectxe2x80x9d includes the conducting metal (e.g., aluminum, copper, tungsten, molybdenum, silver, gold) and also includes a metal interconnect diffusion barrier, such as TaN or TiN, if employed to block the metal from diffusing into the dielectric.
Thus, in one aspect the invention is an integrated circuit structure disposed on a substrate, wherein the structure comprises:
(a) a fluorinated dielectric layer; and
(b) a fluorine diffusion barrier adjacent the fluorinated dielectric layer. The fluorine diffusion barrier comprises doped or undoped silicon in combination with tantalum, tantalum nitride, tantalum silicide, cobalt, cobalt silicide, or a mixture thereof. The fluorine diffusion barrier may be a single layer, and the amount of silicon, if included in the single layer, may be graded. Alternatively, the barrier may be a double layer, or multiple alternating layers, wherein one of the layers (or one of the alternating layers) is silicon. Preferably, the fluorinated dielectric layer is selected from the group of perfluorocyclobutane (PFCB), fluorinated polyethylene, such as polytetrafluoroethylene (PTFE), fluorinated parylene, fluorinated amorphous carbon, and SiO:F. In some fabrication processes, it may be beneficial to include an adhesion promoting layer or nucleation layer interposed between the fluorine diffusion barrier and the fluorinated dielectric layer. Generally, the fluorine diffusion barrier ranges in thickness from about 1 to about 500 xc3x85.
In another aspect, the present invention is a process for preventing diffusion of fluorine from a fluorinated dielectric layer into an interconnect. The process comprises:
(a) providing a fluorinated dielectric layer on a substrate; and
(b) depositing a fluorine diffusion barrier onto the fluorinated dielectric layer, wherein the fluorine diffusion barrier comprises doped or undoped silicon in combination with tantalum, tantalum nitride, tantalum silicide, cobalt, cobalt silicide, or a mixture thereof, wherein at temperatures up to at least 450xc2x0 C., fluorine diffusion is prevented. An adhesion promoting layer or nucleation layer may be deposited onto the fluorinated dielectric layer, and the fluorine diffusion barrier would then be deposited onto the adhesion promoting layer or nucleation layer. Also, the process may include the step of depositing an interconnect onto the fluorine diffusion barrier.
In yet another aspect, the invention is a process for preventing diffusion of fluorine from a fluorinated dielectric layer into an interconnect, wherein the process comprises:
(a) providing a substrate having an interconnect thereon;
(b) depositing a fluorine diffusion barrier onto the interconnect, wherein the fluorine diffusion barrier comprises doped or undoped silicon in combination with tantalum, tantalum nitride, tantalum silicide, cobalt, cobalt silicide, or a mixture thereof; and
(c) depositing a fluorinated dielectric layer onto the fluorine diffusion barrier. At temperatures up to at least 450xc2x0 C., fluorine diffusion is prevented. An adhesion promoting layer or nucleation layer may be deposited onto the interconnect, after step (a), and the fluorine diffusion barrier would then be deposited onto the adhesion promoting layer or nucleation layer.
Other details and features of this invention will become clear from the following examples and the description of the preferred embodiments, taken in conjunction with the accompanying drawings.